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features two digitally controlled, 256-position p otentiometers serial port provides m eans for s etting and r eading both potentiometers resistors c an be c onnected in series to provide increased total resistance 20-pin tssop and 16- pin so packages are available resistive elements are temperature compensated to 0.3 lsb relative linearity standard resistance values: - ds1868b-10 ~ 10k w - ds1868b-50 ~ 50k w - ds1868b-100 ~ 100k w +5v or 3v operation operating temperature range: industrial: -40c to +85c pin description l0, l1 - low end of resistor h0, h1 - high end of resistor w0, w1 - wiper terminal of resistor s out - stacked configuration output rst - serial port reset input dq - serial port data input clk - serial port clock input c out - cascade port output v cc - +5 volt supply gnd - ground connections nc - no internal connection v b - substrate bias voltage dnc - do not connect *all gnd pins must be connected to ground. pin assignment part no. pin - package end - to - end resistance (k ?) ds1 868be-010+ 20 tssop 10 ds1 868be-050+ 20 tssop 50 ds1868be-100+ 20 tssop 100 ds1 868bs-010+ 16 so 10 ds1868bs-050+ 16 so 50 ds1868bs-100+ 16 so 100 ds1868b dual digital potentiometer www. maximintegrated.com 20 - pin tssop (173 - mil) v b dnc h1 l1 w1 rst clk dnc dnc gnd v cc dnc dnc s out w0 h0 l0 c out dnc dq 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ds1868bs 16 - pin so (300 - mil) v b nc h1 l1 w1 rst clk gnd v cc nc s out w0 h0 l0 c out dq 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 19 - 6593; rev 1; 1/14 maxim integrated 1 downloaded from: http:///
ds1868b description the ds1868b dual digital potentiometer chip consists of two digitally controlled solid - state potentiometers. each potentiometer is composed of 256 resistiv e sections. between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. the position of the wiper on the resistor array is set by an 8 - bit value that controls which tap point is connected to the wiper output. communication and control of the device is accomplished via a 3 - wire serial port interface. this interface allows the device wiper position to be read or written. both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. for multiple - device, single - processor environments, the ds1868 b can be cascaded or daisy chained. this feature provides for control of multiple devices over a single 3-wir e bus. the ds1868b is offered in three standard resistance values which incl ude 10 k? , 50 k? , and 100 k? versions. the part is availabl e in 16-pin so (300-mil) and 20-pin (173- mil) tssop packages. operation the ds1868b contains two 256 - position potentiometers whose wiper positions are set by an 8 - bit value. these two 8 - bit values are written to a 17 - bit i/o shift register which is used to store the t wo wiper positions and the stack select bit when the device is powered. a block diagram of the ds1868b is presented in figure 1. communication and control of the ds1868b is accomplished through a 3 - wire serial port interface that drives an internal control logic unit. the 3 - wire serial interface consists of the three input signals: rst , clk, and dq. the rst control signal is used to enable the 3 - wire serial port operation of the device. the rst signal is an active - high input and is required to begin any communication to the ds1868b. the c lk signal input is used to provide timing synchronization for data input and output. the dq signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17 - bit i/o shift register of the ds1868b. figure 9(a) presents the 3 - wire serial port protocol. as shown, the 3 - wire port is inactive when the rst signal input is low. communication with the ds1868b requires the transit ion of the rst input from a low state to a high state. once the 3 - wire port has been activated, data is entered into the part on the l ow to high transition of the clk signal inputs. three - wire serial timing requirements are provided in the timing diagrams of figure 9(b),(c). data written to the ds1868b over the 3 - wire serial interface is stored in the 17 - bit i/o shift register (see figure 2). the 17 - bit i/o shift register contains both 8 - bit potentiometer wiper position values and the stack select bit. the composition of the i/o shift register is pres ented in figure 2. bit 0 of the i/o shift regi ster contains the stack select bit. this bit will be discussed in the section entitled stacked configuration. bits 1 through 8 of the i/o shift register contain the potentiometer - 1 wiper position value. bit 1 will contain the msb of the wiper setting for p otentiometer - 1 and bit 8 the lsb for the wiper setting. bits 9 through 16 of the i/o shift register contain the value of t he potentiometer - 0 wiper position with the msb for the wiper position occupying bit 9 and the lsb bit 16. maxim integra ted .................................................................................................... ......................................................................................... 2 downloaded from: http:///
ds1868b ds1868b block diagram figur e 1 i/o shift register figure 2 transmission of data always begins with the stack select bit follo wed by the potentiometer - 1 wiper position value and lastly the potentiometer-0 wiper position value. when wiper position data is to be written to the ds1868b, 17 bits (or some integer multiple) of data should always be transmitted. transactions which do not send a complet e 17 bits (or multiple) will leave the register incomplete and possibly an error in the desired wiper positions. after a communication transaction has been completed the rst signal input should be taken to a low state to prevent any inadvertent changes to the device shift register. once rst has reached a low state, the contents of the i/o shift register are loaded into the resp ective multiplexers for setting wiper position. a new wiper position will only engage after a rst transition to the inactive state. on device power - up, wipe r position will be random. stacked configuration the potentiometers of the ds1868b can be connected in series as shown in figure 3. this i s referred to as the stacked configuration and allows the user to double the total e nd - to - end resistance of the part. the resolution of the combined potentiometers will remain the same as a s ingle potentiometer but with a total of 512 wiper positions available. device resolution is defined as r tot /256 (per potentiometer); where r tot equals the total potentiometer resist ance. the wiper output for the combined stacked potentiometer will be taken a t the s out pin, which is the multiplexed output of the wiper of potentiometer - 0 (w0) or potentiometer - 1 (w1). the potentiometer wiper selected at the s out output is governed by the setting of the stack select bit (bit 0) of the 17 - bit i/o shift register. if the stack select bit has value 0, the multi plexed output, s out , will be that of the potentiometer - 0 wiper. if the stack select bit has value 1, the multiplexed output , s out , wi ll be that of the potentiometer -1 wiper. maxim integra ted .................................................................................................... ......................................................................................... 3 downloaded from: http:///
ds1868b stacked configuration figure 3 cascade operation a feature of the ds1868b is the ability to control multiple device s from a single processor. multiple ds1868bs can be linked or daisy - chained as shown in figure 4. as a data bit is entered into the i/o shift register of the ds1868b a bit will appear at the c out output after a minimum delay of 50n s. the stack select bit of the ds1868b will always be the first out of the part at the beginning of a transaction. the c out pin will always have the value of the stack select bit (b0) when rst is inactive. cascading multiple devices figure 4 the c out output of the ds1868b can be used to drive the dq input of another ds1868b. whe n connecting multiple devices, the total number of bits transmitted is alw ays 17 times the number of ds1868bs in the daisy chain. an optional feedback resistor can be placed between the c out terminal of the last device and the first ds1868b dq, input thus allowing the contro lling processor to read, as well as, write data, or circularly clock data through the daisy chain. the value of the feedback or isola tion resistor should be in the range from 2 ? to 10k?. when reading data via the c out pin and isolation resistor, the dq line is left f loating by the reading device. when rst is driven high, bit 17 is present on the c out pin, which is fed back to the input dq pin through the isolation resistor. when the clk input transitions low to high, bit 17 is loaded into the first position of the i/o shift register and bit 16 becomes present on c out and dq of the next device. after 17 bits (or 17 times the number of ds1868bs in the daisy chain), the data has shifted completely around and back to its original position. when rst transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded into the wiper - 0, wiper - 1, and stack select bit i/o register. maxim integra ted .................................................................................................... ......................................................................................... 4 downloaded from: http:///
ds1868b absolute and relative linearity absolute linearity, also known as integral nonlinearity, is defined a s the difference between the actual measured output voltage and the expected output voltage. figure 5 presents the test circuit used to measure absolute linearity. absolute l inearity is given in terms of a minimum increment or expected output when the wiper is moved one position. in the case of the test circ uit, a minimum increment (mi) or one lsb would equal 5/256v. the equation for absolute linearity is given as follows: (1) ab solute linearity (inl) al={v o (actual) - v o (expected)}/mi relative linearity, also known as differential nonlinearity, is a measure of error between two adjacent wiper position points and is given in terms of mi by equation (2). (2) relative linearity (dnl) rl={v o (n+1) - v o (n)}/mi figure 6 is a plot of absolute linearity and relative linearit y versus wiper position for the ds1868b at 25 c. the specification for absolute linearity of the ds1868b is 0.75 mi typical. the specification for relative linearity o f the ds1868b is 0.3 mi typical. linearity measurement configuration figure 5 maxim integra ted .................................................................................................... ......................................................................................... 5 downloaded from: http:///
ds1868b ds1868b absolute and relative linearity figure 6 typical application configurations figures 7 and 8 show two typical application configurations for the ds1868b. by connecting the wiper terminal of the part to a high - impedance load, the effects of the wiper resistance is minimized, s ince the wiper resistance can vary from 900? to 2000? , depending on wiper voltage. figure 7 presents t he device connected in a variable gain amplifier. the gain of the circuit on figure 7 is given by the following equation: a v = n- 256 256 + where n = 0 to 255 figure 8 shows the device operating in a fixed gain attenuator w here the potentiometer is used to attenuate an incoming signal. note the resistance r1 is chosen to be much greater than the wiper resistance to minimize its effect on circuit gain. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 lsb tap position linearity vs . tap position inl dnl ds1868b 10k maxim integra ted .................................................................................................... ......................................................................................... 6 downloaded from: http:///
ds1868b variable gain amplifier figure 7 fixed gain attenuator figure 8 maxim integra ted .................................................................................................... ......................................................................................... 7 downloaded from: http:///
ds1868b absolute m aximum ratings* voltage on any pin relative to ground (v b = gnd) ......................................................... -0.5v to +7.0v voltage on any pin when v b = -3.3v ......................................................................... -3.3v to (v cc + 0.5) operating temperature ................................................................................................... .... -40 c to +85 c storage temperature ................................................................................................... ...... -55c to +125c soldering temperature ................................................................................................... ....... 260c for 10s * this is a stress rating only and functional operation of the device at the se or any other conditions above those indicated in the operation sections of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods of tim e may affect reliability. recommended dc operating conditions (- 40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes supply voltage v cc 4.5 2.7 5.5 3.3 v 1 9 input logic 1 v ih +0.7 x vcc v cc + 0.5 v 1, 2 input logic 0 v il -0.5 +0.3 x vcc v 1, 2 ground gnd gnd gnd v 1 resistor inputs l, h, w v b - 0.5 v cc + 0.5 v 2, 9 substrate bias v b -3.3 gnd v 1, 9 dc electrical characteristics (- 40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes supply current i cc 2.1 5 ma 7 input leakage i li -1 +1 m a 11 wiper resistance r w 900 2000 w wiper current i w 1 ma logic 1 output at 2.4v i oh -1 ma 5 logic 0 output at 0.4v i ol 4 ma 5 standby current i stby 0.6 2 m a 8 analog resistor characteristics (- 40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes end - to -end resistor tolerance -20 +20 % 10 integral nonlinearity (inl) -1.6 0.75 +1.6 lsb 3 differential nonlinearity (dnl -0.5 0.3 +0.5 lsb 4 temperature coefficient 750 ppm/c maxim integra ted .................................................................................................... ......................................................................................... 8 downloaded from: http:///
ds1868b capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf ac electrical characteristics (- 40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes clk frequency f clk dc 3.5 mhz 6 width of clk pulse t ch 50 ns 6 data setup time t dc 30 ns 6 data hold time t cdh 10 ns 6 propagation delay time low to high level clock to output t plh 250 ns 6 propagation delay time high to low level t phl 250 ns 6 rst high to clock input high t cc 50 ns 6 rst low from clock input high t hlt 50 ns 6 rst inactive t rlt 125 ns 6 notes: 1. all voltages are referenced to ground. 2. resistor inputs cannot exceed v b - 0.5v in the negative direction. 3. inl is used to determine wiper voltage versus expected voltage as determine d by wiper position. 4. dnl is used to determine the change in voltage between successive tap positions. 5. c out is active regardless of the state of rst . 6. see figure 9(a), (b), and (c). 7. supply current is dependent on clock rate (see figure 11). 8. standby currents apply when rst , dq are in the low- state. 9. when biasing the substrate minimum v b = -3.0v 10% and maximum v cc = 3.0v 10%. 10. valid at +25 c only. 11. digital inputs. maxim integra ted .................................................................................................... ......................................................................................... 9 downloaded from: http:///
ds1868b timing diagrams figure 9 (a) 3- wire serial interface general overview (b) start of communication transaction (c) end of communication transaction maxim integra ted .................................................................................................... ....................................................................................... 10 downloaded from: http:///
ds1868b typical supply current vs. serial clock rate figure 10 maxim integra ted .................................................................................................... ....................................................................................... 11 downloaded from: http:///
ds1868b ds1868b 20 - pin tssop dim min max a mm - 1.10 a1 mm 0.05 - a2 mm 0.75 1.05 c mm 0.09 0.18 l mm 0.50 0.70 e1 mm 0.65 bsc b mm 0.18 0.30 d mm 6.40 6.90 e mm 4.40 nom g mm 0.25 ref h mm 6.25 6.55 phi 0 8 package information for the latest package outline information and land patterns (footprints), go t o www.maximintegrated.com/packages . note t hat a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so w16+6 21 - 0042 90 - 0107 20 tssop u20+2 21 - 0066 90 - 0116 maxim integra ted .................................................................................................... ....................................................................................... 12 downloaded from: http:///
ds1868b revision history revision date description pages changed 2/13 initial release 1/14 removed future product notation in ordering information 1 13 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the ci rcuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated, 160 rio robles, san jose, ca 95134 1 - 408 - 601 - 1000 201 4 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. downloaded from: http:///

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